Advances in semiconductor technology have enabled the dimensions of semiconductor devices to be continuously reduced. As a result, the properties and performances of transistors are affected by the dimension shrinkage. To further improve the properties and performances of transistors, strain engineering has been introduced to the manufacturing of transistors. By applying compressive stress on a channel region of a transistor, hole mobility in the channel region may be improved. By applying tensile stress on the channel region of a semiconductor, electron mobility in the channel region may be improved.
Since electrons have higher mobility than holes in single-crystal silicon, in conventional semiconductor manufacturing, strain engineering is often used to improve hole mobility in PMOS transistors. The carrier mobility in PMOS transistors can thus be comparable to the carrier mobility in NMOS transistors. Strained materials are often used to form the source and drain regions of a PMOS transistor such that compressive stress may be applied on the channel region of the PMOS transistor to improve the hole mobility in the channel region. Specifically, the process to form the source and drain regions using strained materials includes the following process. First, trenches are formed in the substrate on both sides of the gate structure of the PMOS transistor. Further, the trenches are filled with a strained material. The trenches may function as the source region of the PMOS transistor. The lattice constant of the strained material is often greater than the lattice constant of the material in the channel region. Thus, the strained material can apply compressive stress on channel region of the PMOS transistor. SiGe has been commonly used as the strained material for the PMOS transistor. In conventional semiconductor manufacturing, SiC is often used as the strained material for the source and the drain regions of an NMOS transistor to further improve the carrier mobility of the NMOS transistor.
However, source and drain regions formed using conventional semiconductor manufacturing processes may be highly defective on the surfaces of the source and the drain regions. As a result, contact resistance of a source region or a drain region may be undesirably high. Thus, properties and performances of the transistors formed through conventional semiconductor manufacturing may be adversely affected.